The present invention relates to an integrated circuit chip comprising two or more passive components (resistors and/or capacitors). More specifically, the present invention relates to a novel configuration and arrangement for the components in the chip, and to a novel method of fabricating the chip.
Currently, passive component integrated circuit chips that contain both capacitors and resistors are configured with the capacitors and resistors in a side-by-side relationship. For example, a capacitor structure may be fabricated on an alumina substrate, and a resistor may be fabricated next to the capacitor structure. This results in either a relatively large surface area for the chip, or a low maximum capacitance value. Furthermore, the fabrication of the chip is complicated by the need to print the resistors around and/or between the capacitor(s).
It is therefore desired to provide a passive component integrated circuit chip that allows for a more compact structure (smaller surface area) and higher capacitance values than have heretofore been possible. It would also be desirable to simplify the fabrication process, thereby reducing the manufacturing cost of these devices.